1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically to superconducting analog-to-digital delta-sigma modulators employing quantum accurate digital-to-analog converters for noise reduction.
2. Description of Related Art
Delta-sigma analog-to-digital converter (ADC) performance depends on accurate feedback and short comparator decision time. Superconducting circuits are an attractive technology for use in delta-signal converters because they can achieve both of these design constraints due to inherent quantization and picosecond timescale switching of the Josephson junction. Comparator performance can be characterized in terms of both sensitivity and decision time. Sensitivity depends on thermal noise and has been a primary focus for Josephson comparators in the past. The delta-sigma architecture is tolerant of sensitivity errors due to feedback, but the feedback mechanism requires a short decision time, ideally a small fraction of the sample period.
FIG. 1 shows a schematic of a proven first order superconductor delta-sigma modulator. An analog input signal 11 is inductively coupled through an inductor 12 to a quantum comparator formed by two series Josephson junctions 13 and 14. A clock signal of frequency clk/2 is applied to another Josephson junction 15 to provide a DC offset V=φ0·clk/2 to the comparator, where φ0=h/2e is a fundamental physical unit called the single-flux-quantum. This value of DC offset ensures that the comparator triggers every other clock cycle, i.e. to allow the circuit to dither about an operating point of 1-0-1-0 . . . (etc.). Junctions 13 and 14 constitute a Josephson comparator that produces a digital output 16 in the form of a bit stream of binary ones and zeroes, with a binary one defined as a voltage pulse (or single-pulse quantum) generated by a Josephson junction. Clock signal clk is applied to junction 13 so that every clock cycle, either junction 13 or junction 14 will trigger, depending on the amount of current in the inductor 12. For example, junction 13 may trigger when the comparator is below a current threshold, producing a binary zero at output 16. At another clock cycle, when inductor current exceeds the current threshold, junction 14 may trigger to produce a binary one at output 16. In the latter case, the voltage pulse is also applied as back emf which reduces current flow into the comparator, providing implicit feedback −φ0 at the same level as the output signal.
FIG. 2 shows a schematic of a proven second order superconductor delta-sigma modulator. An analog input signal 21 is coupled directly to the circuit across a resistor 22 to provide a desired voltage offset. An inductor 23 forms a first integrator with resistor 22, and this integrator is cascaded with a second integrator formed by resistor 24 and inductor 25. The output of the second integrator is coupled to a quantum comparator formed by series Josephson junctions 26 and 27. These junctions behave as in the comparator of FIG. 1 to produce a digital bit stream at output 29. As long as signal current in the second integrator remains below the threshold of the comparator, junction 26 will trigger with each clock cycle to produce a binary zero at output 29. When the signal current exceeds the threshold, junction 27 triggers, producing a binary one at the output, and generating an implicit feedback of −φ0 into the second integrator. This feedback signal is amplified in an explicit feedback loop by a quantum digital-to-analog converter (DAC) 28 having a gain of fifty φ0 to decrement the current in the first integrator. The magnitude of the gain in the feedback loop is selected depending on a desired level of signal isolation between the first and second integrators.
The foregoing second order delta-sigma ADC clocked at 20 GHz can achieve an oversampling ratio of 2000 with respect to a 0-10 MHz signal band. The ADC can approach 20 dB/decade quantization noise suppression, in keeping with ideal quantization noise theory. Overall signal-to-noise ratio represents the current state of the art. ADC converters having performance beyond the state of the art would improve the performance of existing systems such as horizon-search radar, and enable new missions such as broadband digitization of the spectrum for space-based electronic surveillance. The keys to high performance in delta-sigma ADCs are high oversampling clock rates and accuracy in the feedback DAC. Thus, superconductor ADC modulators may be advanced beyond the state of the art by optimizing the design of the DAC converter that is used in the feedback loop.